🤗 New Investment: DYNANIC is accelerating next-generation programmable chips for AI and high-speed computing
We are excited to announce that Tensor Ventures invested in DYNANIC, a deep-tech startup building solutions that unlock the full potential of programmable chips for high-performance applications like AI, virtual reality, and next-generation networking.
Founded by Pavol Korček, Lukáš Kekely, and Jan Kořenek as a spin-out from Brno University of Technology, DYNANIC simplifies how programmable chips are used and integrated — making them far more accessible, efficient, and performant across computing environments where speed and flexibility are essential.
The company has secured €550,000 in pre-seed funding from Tensor Ventures alongside a group of experienced angel investors, including industry veterans from Dell, AMD, Intel, and Hewlett Packard Enterprise. This investment marks the first deployment from Tensor’s second deep-tech fund and will accelerate product development, market expansion, and technology maturation.
At its core, DYNANIC is driven by a clear purpose: to democratize access to programmable computing — empowering developers, companies, and platforms to harness flexible hardware without specialized expertise.
DYNANIC: Making Programmable Chips Practical for the AI Era
High-performance computing is evolving fast. Today’s workloads — from AI inference engines to real-time analytics and virtual reality — demand not just raw compute but adaptable compute that can be reconfigured in the field to meet changing requirements.
Programmable chips such as FPGAs (Field-Programmable Gate Arrays) offer this flexibility, but they have historically been hard to program and integrate. This has kept them on the sidelines of many modern applications — despite their performance and efficiency advantages.
DYNANIC is changing that.
By building tools and frameworks that simplify how programmable chips are used, the company makes advanced chip technologies accessible to teams without deep hardware programming expertise, and unlocks performance benefits previously available only to a narrow class of specialists.
Why DYNANIC?
Programmable chips have long been a performance frontier — capable of delivering acceleration, power efficiency, and adaptability. Yet unlocking that value normally requires teams of experts writing low-level code and managing complex toolchains.
This complexity has limited their adoption in emerging compute areas that urgently need them, especially:
AI workloads where latency and throughput are critical
High-speed networking such as 100 Gbps and 400 Gbps links
Edge and data center acceleration where flexibility matters
DYNANIC addresses this challenge by offering abstractions and tooling that make programmable chips as accessible as software — dramatically shortening time to value and reducing reliance on scarce hardware programmers.
What’s Their Story?
DYNANIC was born out of research at Brno University of Technology, where its founders spent decades developing deep expertise in programmable logic and high-speed computing.
Formerly known as BrnoLogic, the team combined academic rigor with a practical mission: make programmable chips usable in real world applications without the prohibitive complexity they’ve traditionally required.
Co-founder Pavol Korček and his team saw programmable chips as a generational opportunity — a way to give systems unparalleled flexibility and performance — if only the barriers to use could be removed.
With this vision, they built a technology stack that automatically optimizes and adapts chip configurations, enabling customers to customize performance without deep FPGA expertise.
A New Approach to Programmable Chips
What makes DYNANIC different is its focus on usability without compromise.
Programmable chips are powerful precisely because they can be reconfigured after production. But that flexibility also makes them hard to work with.
DYNANIC’s approach:
Abstracts the complexity of FPGA programming into higher-level tooling
Automates optimization, selecting the best configurations for a given workload
Boosts performance and throughput, especially for networking and AI-related tasks
Integrates with existing infrastructure so companies can adopt without rewriting systems.
This combination gives organizations the performance of programmable logic with the accessibility of general-purpose software — a rare and valuable blend.
How Have They Grown?
Since launching, DYNANIC has already demonstrated notable progress.
Its technology has been licensed and adopted by major programmable chip manufacturers — including leading names such as Intel and AMD — and used by companies like Kakao Corp and Kaloom Networks to improve server efficiency and throughput.
With the support of Tensor Ventures and experienced angels, the company is now scaling its product, targeting broader adoption in high-performance computing segments and among global hyperscaler customers.
The investment will enable further refinement of the platform, acceleration of advanced networking technologies (including next-generation 800 Gbps solutions), and expansion into new markets where reconfigurable computing offers clear advantages.
Why We’re Invested
At Tensor Ventures, we invest in deep-tech companies that bring computational innovation into the physical and digital infrastructure of tomorrow.
DYNANIC reflects exactly that mission.
Programmable chips are a cornerstone of future computing — especially as AI workloads push traditional architectures to their limits. But their promise has been constrained by accessibility and tooling gaps.
DYNANIC bridges that gap, making advanced reconfigurable hardware practical for real-world use cases without requiring rare engineering skills.
We believe this technology has the potential to:
reshape how edge and data-center acceleration is achieved
unlock performance efficiencies for AI and networking
broaden the addressable market for programmable hardware
This investment is a step toward a world where programmable computing is no longer a niche but a foundational layer of next-generation systems.
And we’re proud to support DYNANIC on that journey.
Really strong thesis on accessiblity in FPGA tooling. The gap between FPGA capability and practical adoption has always been that last-mile problem of specialized knowledge. Seeing traction with Intel and AMD customers is validating, since those ecosystems are notoriusly tough to crack. The 800 Gbps networking angle is especially intresting as inference workloads push beyond what fixed ASICs can handle economically.